1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to the structure of a bipolar transistor.
2. Description of the Prior Art
Transistors have been decreased in size to obtain high-speed, high-density LSIs. In particular, in a bipolar transistor, with a decrease in emitter size, a variation in emitter area and a decrease in cut-off frequency caused by an increase in current density have been posed as problems. For this reason, methods of increasing an emitter area without changing a base area are studied, and one of these methods has been proposed in Japanese Patent Laid-Open No. 61-112378. In a transistor according to this prior art, a base contact region is arranged at the central portion of the transistor, and an annular emitter region is formed around the base contact region. In this transistor, an emitter region having an area twice that of a general transistor can be assured without increasing a base area. For this reason, the transistor of the above-mentioned first prior art allows a larger current to follow.
FIG. 1 is a view showing the above structure. A silicon dioxide film 22 and a silicon nitride film 23 are formed on a silicon substrate 21, and a polysilicon film 24 is formed on these films through openings formed therein. Boron and arsenic are doped in the polysilicon film 24, and then thermally diffused in the silicon substrate 21 to from a base 25 and an emitter 26. A graft base 27 is formed in advance by ion implantation of boron.
Note that reference numeral 28 denotes an insulating film; 29, a base electrode; and 30, an emitter electrode. In this manner, the transistor is constituted as a transistor having a ring-like emitter.
In Japanese Patent Laid-Open No. 64-15973, an annular emitter region formed by the same method as that of forming the above structure is described.
However, the following problem is posed in the above conventional transistor having the annular emitter. More specifically, boron and arsenic doped in the polysilicon film 24 are thermally diffused in the monocrystalline substrate 21 so as to form the base 25 and the emitter 26, thereby forming the annular emitter. However, in this method, each impurity cannot be easily diffused with good controllability. For this reason, desired base and emitter cannot be easily formed, and a variation in element becomes large.
The same problem as described above is also posed in a transistor described in Japanese Patent Laid-Open No. 64-15973 using a method of forming a base region and then forming an emitter region in the base region.
Therefore, the following structure described in Japanese Patent Application No. 3-79388 is considered. That is, an epitaxial base layer is formed using a selective epitaxial growing method such as a UHV/CVD (Ultra High Vacuum/Chemical Vapor Deposition) method, and an emitter is formed in the epitaxial base layer.
More specifically, as shown in FIG. 2, an n-type low-resistance region 32 is formed on a p-type silicon substrate 31, and an n-type silicon epitaxial layer 33 is formed on the n-type low-resistance region 32. Reference numeral 34 denotes an isolation region; and 35, an insulating interlayer. Reference numeral 36 denotes a collector extracting polysilicon layer; 37, a p.sup.+ -type polysilicon layer for connecting an external base to a base electrode 38; and 39, an insulating film. Reference numeral 40 denotes a side wall for achieving insulation; 41, an epitaxial base layer; 42, a polysilicon film for connecting the epitaxial base layer 41 to the polysilicon layer 37. Reference numeral 43 denotes an emitter extracting polysilicon film; and 44, an emitter diffusion layer. Reference numeral 45 denotes an emitter electrode; and 46, a collector electrode.
In the above transistor, the n-type polysilicon film 37 is used in place of the emitter diffusion layer 44, and an impurity is thermally diffused from the polysilicon layer 37 into the epitaxial base layer 41. In this case, an annular emitter diffusion layer can be formed around the epitaxial base layer 41. When the transistor is formed by this method, it is apparent that the base can be formed with good controllability in concentration and thickness. Since the base can be decreased in size in the horizontal direction, a bipolar transistor having a high cut-off frequency and a small parasitic capacitance can be formed.
However, the following problems are posed. That is, first, the epitaxial base layer 41 is grown, and, at the same time, the polysilicon film 42 is grown on the bottom surface of the n-type polysilicon film 37. For this reason, if an n-type impurity is not satisfactorily diffused, a base-emitter junction is formed in the polysilicon film 42, thereby causing an increase in base leakage current.
Second, since the emitter is formed under the overhung portion of the n-type polysilicon layer 37, the concentration of the silicon epitaxial layer 33 immediately below the formed emitter diffusion layer cannot be selectively increased by ion implantation. For this reason, a Kirk effect easily occurs, thereby degrading the high-frequency characteristics of the transistor.
Therefore, the method of manufacturing a transistor shown in FIG. 2 cannot be applied to manufacture a transistor having an annular emitter diffusion layer without any problem, and the method cannot be actually applied.